A liquid crystal display device is a flat-panel display device which has excellent characteristics including high resolution, small thickness, light weight, and low power consumption. Its market size has expanded recently with improvements in display performance and production capacity as well as improvements in price competitiveness against other types of display device.
A twisted nematic (TN) liquid crystal display device which has conventionally been in common use has liquid crystal molecules with positive dielectric anisotropy placed between upper and lower substrates in such a way that long axes of the liquid crystal molecules are oriented substantially parallel to substrate surfaces and twisted 90 degrees along a thickness direction of a liquid crystal layer. When a voltage is applied to the liquid crystal layer, the liquid crystal molecules rise parallel to the electric field, becoming free from the twisted alignment. The TN liquid crystal display device controls transmitted light quantity using rotary polarization changes resulting from orientation changes of the liquid crystal molecules by the voltage.
The TN liquid crystal display device allows wide manufacturing margins and high productivity. Meanwhile, it has problems with display performance, especially with viewing angle characteristics. Specifically, when a display surface of the TN liquid crystal display is viewed obliquely (Hereinafter, a state in which a display surface or an image is viewed obliquely is sometimes referred to as “oblique viewing state.”, the display contrast ratio drops considerably. Consequently, even if an image clearly presents a plurality of gradations from black to white when viewed straight-on (Hereinafter, a state in which a display surface or an image is viewed straight-on is sometimes referred to as “straight-on viewing state.”), luminance differences between gradations appear very unclear when the image is viewed obliquely. Besides, a phenomenon (so-called gradation reversal) that a portion which appears dark when viewed straight-on appears brighter when viewed obliquely also raises a problem.
In order to improve the viewing angle characteristics of the TN liquid crystal display device, some liquid crystal display devices have been developed recently, including an in-plane switching (IPS) liquid crystal display device, a multi-domain vertically aligned (MVA) liquid crystal display device, an axial symmetric micro-cell (ASM) display device, and other liquid crystal display devices.
A liquid crystal display device employing any one of the novel modes described above (wide viewing angle modes) solves the concrete problems with viewing angle characteristics. Specifically it is free of the problems that the display contrast ratio drops considerably or display gradations are reversed when the display surface of the TN liquid crystal display is viewed obliquely.
Today, however, under such circumstances that display quality of a liquid crystal display device continues to be improved, such a new problem with viewing angle characteristics has emerged that gamma characteristics in a straight-on viewing state differs from those in an oblique viewing state. That is, this is a problem associated with viewing angle dependency of gamma characteristics. Gamma characteristics mean gradation dependency of display luminance. The difference between gamma characteristics in a straight-on viewing state and those in an oblique viewing state means that a halftone display state differs depending on angles at which a display surface or an image is viewed. This makes problems especially in case of displaying images such as photographs or displaying television broadcasts and the like.
The viewing angle dependency of gamma characteristics is more prominent in the MVA mode and the ASM mode than in the IPS mode. Meanwhile, it is more difficult to produce an IPS panel which provides a high contrast ratio when viewed straight-on with high productivity than an MVA or ASM panel. Thus, it is desirable to reduce the viewing angle dependency of gamma characteristics especially in the MVA or ASM mode.
The inventors have proposed in Japanese Unexamined Patent Publication No. 62146/2004 (Tokukai 2004-62146; published on Feb. 26, 2004) a multi-pixel driving method as a method for reducing the viewing angle dependency of gamma characteristics. First, the multi-pixel driving method is described with reference to the figures.
The multi-pixel driving method is a technique which reduces the viewing angle characteristics (viewing angle dependency of gamma characteristics) by forming a single display pixel by using two or more sub-pixels having different luminance levels. First, a principle of the method will be briefly described.
FIG. 11 shows gamma characteristics (gradation (voltage)-luminance) of a liquid crystal display panel. A solid line of FIG. 11 represents gamma characteristics in a straight-on viewing state in a normal driving method (in which a single display pixel is not divided into a plurality of sub-pixels). In this case, the best viewability is achieved. Further, a dotted line of FIG. 11 represents gamma characteristics in an oblique viewing state in the normal driving method. In this case, there is a difference between gamma characteristics in a straight-on viewing state and those in an oblique viewing state, and the difference becomes small in a portion indicating a high or low luminance level and becomes large in a portion indicating a halftone luminance level.
In the multi-pixel driving method, for obtaining a target luminance level in the single display pixel, display control is performed so that an average luminance level of the plurality of sub-pixels having different luminance levels is the target luminance level. Moreover, as with the normal driving method, gamma characteristics in a straight-on viewing state in the multi-pixel driving method is set so that the best viewability is achieved. Meanwhile, setting of viewability in an oblique viewing state in the multi-pixel driving method is explained. For example, for obtaining a target halftone luminance level at which a luminance difference has conventionally been large, display is performed in that areas of the sub-pixels which are near the high and low luminance levels at which the luminance difference is small. Then, a halftone luminance level of the entire pixel is obtained from an average luminance level of the sub-pixels, so that the luminance difference becomes small. Thus, as represented by a dashed line in FIG. 11, gamma characteristics of a liquid crystal panel are obtained.
Next, FIG. 12 shows an example of an arrangement of a liquid crystal display device which performs multi-pixel driving. As shown in FIG. 12, a pixel 10 corresponding to a single display pixel is divided into sub-pixels 10a and 10b. The sub-pixel 10a has a sub-pixel electrode 18a, and the sub-pixel 10b has a sub-pixel electrode 18b. Connected to the sub-pixel 10a are a TFT (thin film transistor) 16a and an auxiliary capacitor (CS) 22a. Connected to the sub-pixel 10b are a TFT 22b and an auxiliary capacitor 22b. FIG. 12 shows an example of a pixel structure in which the single display pixel is divided into the two sub-pixels. Specifically, FIG. 12 shows a structure in which the sub-pixels have substantially the same area and are divided and arranged in a vertical direction. However, an effect of multi-pixel driving is not limited to the dividing method of FIG. 12. The sub-pixels may have substantially the same area as shown in FIG. 12 or may have different areas. Specifically, an area of a sub-pixel whose luminance level is high in a halftone display state may be made smaller or larger than that of a sub-pixel whose luminance level is low in a halftone display state. In view of reducing viewing angle characteristics, it is preferable that the area of the sub-pixel whose luminance level is high in a halftone display state be smaller than that of the sub-pixel whose luminance level is low in a halftone display state. Further, the sub-pixels having different luminance levels in a halftone display state do not need to be divided and arranged in a vertical direction. Instead, the sub-pixels may be arranged along a reference axis based on a pixel line in a horizontal direction. This arrangement is preferable in terms of display quality because a distribution of display polarities of the sub-pixels takes the form of dot reversal. FIGS. 17(a) and 17(b) show examples of arrangements of sub-pixels disposed over a plurality of pixels. Open circles “o” of FIGS. 17(a) and 17(b) represent sub-pixels whose display luminance levels are high. A plus sign “+” or a minus sign “−” enclosed in each of the open circles represents an electric polarity of each of the pixels. (When a potential of the pixel (sub-pixel) is higher than that of a counter electrode, the plus sign is used. When the potential of the pixel (sub-pixel) is lower than that of the counter electrode, the minus sign is used.)
FIG. 17(a) shows a sub-pixel arrangement based on the arrangement of FIG. 12, and FIG. 17(b) a sub-pixel arrangement based on the foregoing preferred arrangement. In FIG. 17(a), the sub-pixels whose luminance levels are high in a halftone display state are arranged checkerwise. (Although a luminance center of the pixel does not correspond to that of the sub-pixels, the sub-pixels are highly dispersed within a screen.), and the bright sub-pixels having positive (+) or negative (−) display polarities are arranged in horizontal linear groups. That is, the arrangement of the sub-pixels having high luminance levels takes the form of line reversal. In FIG. 17(b), on the contrary, the sub-pixel having high luminance levels are arranged in the center of the pixel (The luminance center of the pixel corresponds to that of the sub-pixels), and the display polarities of the sub-pixels having high luminance levels takes the same form of dot reversal as the display polarity of the pixel. Thus, the sub-pixel arrangement of FIG. 17(b) is more preferable than that of FIG. 17(a).
Furthermore, a shape of each of the sub-pixels is not limited to a rectangle. Especially, in case of the MVA mode, the shape may be a triangle, a rhombus, or other shapes. This arrangement is preferable in terms of a panel aperture ratio (see FIG. 17(c)).
A gate electrode of the TFT 16a and a gate electrode of the TFT 16b are connected to a common (the same) scanning line 12, and a source electrode of the TFT 16a and a source electrode of the TFT 16b are connected to a common (the same) signal line 14. The auxiliary capacitors 22a and 22b are connected to an auxiliary capacitance wire (CS bus line) 24a and an auxiliary capacitance wire 24b, respectively.
The auxiliary capacitor 22a includes an auxiliary capacitance electrode electrically connected to the sub-pixel electrode 18a, an auxiliary capacitance counter electrode electrically connected to the auxiliary capacitance wire 24a, and an insulative layer (not shown) provided between the auxiliary capacitance electrode and the auxiliary capacitance counter electrode. The auxiliary capacitor 22b includes an auxiliary capacitance electrode electrically connected to the sub-pixel electrode 18b, an auxiliary capacitance counter electrode electrically connected to the auxiliary capacitance wire 24b, and an insulative layer (not shown) provided between the auxiliary capacitance electrode and the auxiliary capacitance counter electrode. The auxiliary capacitance counter electrode of the auxiliary capacitor 22a and the auxiliary capacitance counter electrode of the auxiliary capacitor 22b are independent of each other and are arranged so as to receive different auxiliary capacitance counter voltages from the auxiliary capacitance wires 24a and 24b, respectively.
Furthermore, FIGS. 13(a) to 13(f) show driving signals of the liquid crystal display device of FIG. 12. FIG. 13(a) shows a voltage waveform Vs of the signal line 14. FIG. 13(b) shows a voltage waveform Vc of the auxiliary capacitance wire 24a. FIG. 13(c) shows a voltage waveform Vcsb of the auxiliary capacitance wire 24b. FIG. 13(d) shows a voltage waveform Vg of the scanning line 12. FIG. 13 shows (e) a voltage waveform Vlca of the sub-pixel electrode 18a. FIG. 13(f) shows a voltage waveform Vlcb of the sub-pixel electrode 18b. Further, a dotted line of each of FIGS. 13(a) to 13(f) indicates a voltage waveform COMMON (Vcom) of a counter electrode (not shown in FIG. 12).
First, at time T1, a voltage of Vg changes from VgL to VgH, so that the TFT 16a and the TFT 16b are simultaneously put in a conductive state (ON state). In this way, a voltage Vs of the signal line 14 is transferred to the sub-pixel electrodes 18a and 18b, so that the sub-pixels 10a and 10b are charged. Similarly, the auxiliary capacitor 22a of the sub-pixel 10a and the auxiliary capacitor 22b of the sub-pixel 10b are charged by means of the signal line 14.
Next, at time T2, the voltage Vg of the scanning line 12 changes from VgH to VgL, so that the TFT 16a and the TFT 16b are simultaneously put in a nonconductive state (OFF state). In this way, the sub-pixels 10a and 10b and the auxiliary capacitors 22a and 22b stop being charged, so that all of the sub-pixels 10a and 10b and the auxiliary capacitors 22a and 22b are electrically insulated from the signal line 14. Right after this, due to a pull-in effect caused by parasitic capacitances and the like of the TFT 16a and the TFT 16b, a voltage Vlca of the sub-pixel electrode 18a and a voltage Vlcb of the sub-pixel electrode 18b decrease by substantially the same voltage Vd, so thatVlca=Vs−Vd andVlcb=Vs−Vd.Further, at this time, a voltage Vcsa of the auxiliary capacitance wire 24a and a voltage of Vcsb of the auxiliary capacitance wire 24b are such thatVcsa=Vcom−Vad andVcsb=Vcom+Vad.
At time T3, the voltage Vcsa of the auxiliary capacitance wire 24a connected to the auxiliary capacitor 22a changes from Vcom−Vad to Vcom+Vad, and the voltage Vcsb of the auxiliary capacitance wire 24b connected to the auxiliary capacitor 22b changes from Vcom+Vad to Vcom−Vad. In accordance with these voltage changes, the voltage Vlca of the sub-pixel electrode 18a and the voltage Vlcb of the sub-pixel electrode 18b change so thatVlca=Vs−Vd+2×K×Vad andVlcb=Vs−Vd−2×K×Vad.However, K=CCS/(CLC(V)+CCS), where CLC(V) represents an electrostatic capacitance value of a liquid crystal capacitor of each of the sub-pixels 10a and 10b, and a value of CLC(V) depends on an effective voltage (V) applied to a liquid crystal layer of each of the sub-pixels 10a and 10b. Further, CCS represents an electrostatic capacitance value of each of the auxiliary capacitors 22a and 22b. 
At time T4, Vcsa changes from Vcom+Vad to Vcom−Vad, and Vcsb changes from Vcom−Vad to Vcom+Vad. Further, Vlca changes from Vlca=Vs−Vd+2×K×Vad to Vlca=Vs−Vd, and Vlcb changes from Vlcb=Vs−Vd−2×K×Vad to Vlcb=Vs−Vd.
At time T5, Vcsa changes from Vcom−Vad to Vcom+Vad, and Vcsb changes from Vcom+Vad to Vcom−Vad, only by twice as much as Vad. Further, Vlca changes from Vlca=Vs−Vd to Vlca=Vs−Vd+2×K×Vad, and Vlcb changes from Vlcb=Vs−Vd to Vlcb=Vs−Vd−2×K×Vad.
Vcsa, Vcsb, Vlca, and Vlcb alternately repeat the changes at T3 and T5. Intervals or phases at which T3 and T5 are repeated may be adjusted appropriately in view of methods (polarity reversal method and other methods) for driving liquid crystal display devices and display states (flickering, rough display, and other states). (For example, the intervals at which T3 and T5 are repeated can be set to 0.5 H, 1 H, 2 H, 4 H, 6 H, 8 H, 10 H, 12 H, or the like (1 H is a single period of horizontal writing time).) This repetition continues until the pixel 10 is rewritten next time, i.e., until time equivalent to T1. Therefore, an effective value of the voltage Vlca of the sub-pixel electrode 18a and an effective value of the voltage Vlcb of the sub-pixel electrode 18b are such thatVlca=Vs−Vd+K×Vad andVlcb=Vs−Vd−K×Vad.
Consequently, an effective voltage V1 applied to the liquid crystal layer of the sub-pixel 10a and an effective voltage V2 applied to the liquid crystal layer of the sub-pixel 10b are such thatV1=Vlca−Vcom andV2=Vlcb−Vcom,that is,V1=Vs−Vd+K×Vad−Vcom andV2=Vs−Vd−K×Vad−Vcom.
Therefore, a difference ΔV12 (=V1-V2) between the effective voltage applied to the liquid crystal layer of the sub-pixel 10a and the effective voltage applied to the liquid crystal layer of the sub-pixel 10b becomes ΔV12=2×K×Vad, so that different voltages can be applied to the sub-pixels 10a and 10b respectively.
FIG. 14 shows an equivalent circuit of the arrangement of FIG. 12. Because a capacitance of a counter electrode COMMON is very high, impedance R from a connection point P against an inside of the counter electrode COMMON is very high, the connection point P being a point at which counter electrodes of sub-pixel electrodes 18a and 18b of liquid crystal capacitors CLC are connected. Therefore, when the TFT 16a and the TFT 16b are in an OFF state, a series circuit is formed which runs from the auxiliary capacitance wire 24a through the auxiliary capacitor 22a, the liquid crystal capacitor CLC of the sub-pixel 10a, the liquid crystal capacitor CLC of the sub-pixel 10b, and the auxiliary capacitor 22b in this order to the auxiliary capacitance wire 24b. This causes a current ia to be equal to a current ib, the current ia flowing from the auxiliary capacitance wire 24a into the auxiliary capacitor 22a, the current ib flowing from the auxiliary capacitor 22b into the auxiliary capacitance wire 24b. The currents ia and ib are equal also when flowing in the opposite directions.
Accordingly, as shown in FIG. 15, a single capacitor PANEL is formed assuming that the liquid crystal capacitor CLC of the sub-pixel 10a and the liquid crystal capacitor CLC of the sub-pixel 10b are serially connected. Moreover, a series circuit 100 is formed assuming that the auxiliary capacitor 22a and the auxiliary capacitor 22b are serially connected on both sides of the capacitor PANEL, and the series circuit 100 is charged and discharged. However, at a point which corresponds to the connection point P and lies between electrodes of the capacitor PANEL, a potential of the series circuit 100 is fixed at the potential Vcom of the counter electrode COMMON.
The series circuit 100 is charged and discharged by controlling potentials of the auxiliary capacitance wires 24a and 24b as shown in FIGS. 13(a) and 13(b). In FIG. 15, in order to generate the potentials of the auxiliary capacitance wires 24a and 24b, four bipolar transistors Tr1 to Tr4 are used as switches to cause a charge-discharge current of the series circuit 100 to flow from a high voltage source VIN and a low voltage source GND while alternately reversing the direction. The transistor Tr1 is an NPN-type transistor whose collector is connected to the voltage source VIN. The transistor Tr2 is a PNP-type transistor whose collector is connected to the voltage source GND. An emitter of the transistor Tr1 and an emitter of the transistor Tr2 are connected to each other. The transistor Tr3 is an NPN-type transistor whose collector is connected to the voltage source VIN. The transistor Tr4 is a PNP-type transistor whose collector is connected to the voltage source GND. An emitter of the transistor Tr3 and an emitter of the transistor Tr4 are connected to each other. The series circuit 100 is provided between the emitters of the transistors Tr1 and Tr2 and the emitters of the transistors Tr3 and Tr4.
While Vcsa>Vcsb in FIGS. 13(b) and 13(c), the transistors Tr1 and Tr4 are put in an ON state, and the transistors Tr2 and Tr3 are put in an OFF state, so that a current flows in a direction A of FIG. 15. While Vcsa<Vcsb in FIGS. 13(b) and 13(c), the transistors Tr1 and Tr4 are put in an OFF state, and the transistors Tr2 and Tr3 are put in an ON state, so that a current flows in a direction B of FIG. 15. In order to perform push-pull operation of the transistors Tr1 and Tr2 and push-pull operation of the transistors Tr3 and Tr4, a pulse signal CS 1 is inputted through a buffer 101 into a base of the transistor Tr1 and a base of the transistor Tr2. A pulse signal CS2 is inputted through a buffer 102 into a base of the transistor Tr3 and a base of the transistor Tr4. The pulse signals CS1 and CS2 are signals whose phases are opposite to each other.
In the circuit of FIG. 15, for example, when a current flows in the direction A, the potential of the auxiliary capacitance wire 24a gradually increases and the potential of the auxiliary capacitance wire 24b gradually decreases while the transistors Tr1 and Tr4 are put in an ON state. Therefore, in order to keep the transistors Tr1 and Tr4 in an ON state until the potential Vcsa of the auxiliary capacitance wires 24a and the potential Vcsb of the auxiliary capacitance wires 24b become target potentials, a potential higher than a predetermined value with respect to an emitter potential needs to be supplied to the base of the transistor Tr1 and a potential lower than the predetermined value with respect to the emitter potential needs to be supplied to the base of the transistor Tr4. That is, a pulse potential of the pulse signal CS1 is set to a potential at least 0.7 V higher than a target value of Vcsa, and a pulse potential of the pulse signal CS2 is set to a potential at most 0.7 V lower than a target value of Vcsb. For example, when the pulse potential of the pulse signal CS1 is 0.7 V higher than the target value of the Vcsa and the pulse potential of the pulse signal CS2 is 0.7 V lower than the target potential of Vcsb, the auxiliary capacitance wire 24a reaches the target value of Vcsa in a pulse period of the pulse signal CS1 and the auxiliary capacitance wire 24b reaches the target value of Vcsb in a pulse period of the pulse signal CS2. At this point, the transistor Tr1 and Tr4 are put in an OFF state, so that charging and discharging are completed.
However, in an initial point of the pulse period of the pulse signals CS1 or CS2, a high potential is applied between the base and emitter of the transistor Tr1 or Tr4, so that a collector current of-the transistor Tr1 or Tr4 is very high in the initial point of the pulse period. Further, when a current flows in the direction A, there stands the following magnitude relation in potential: 0<target value of Vcsb<target value of Vcsa<VIN (A “voltage source” sign is substituted for a “potential” sign). Then, a voltage of VIN-Vcsa is applied between the collector and emitter of the transistor Tr1, and a voltage of Vcsb-0 is applied between the collector and emitter of the transistor Tr4. Therefore, a voltage between the collector and emitter of the transistor Tr1 or Tr4 is very high in an initial point of a period during which a current flows. Therefore, in the initial point of the pulse period, power consumption represented by a product of the collector voltage and the collector-emitter voltage is very high. Moreover, this happens per unit time twice as many times as frequencies of Vcsa and Vcsb. This generates a large amount of heat in the transistors Tr1 and Tr4 and raises their temperatures. The same applies to the transistors Tr2 and Tr3.
Accordingly, in order to solve this problem, an arrangement of FIG. 16 may be adopted. In FIG. 16, transistors FET1 to FET4 are used instead of the transistors Tr1 to Tr4 of FIG. 15. The transistors FET1 and FET3 are P-channel MOSFETs, and the transistors FET2 and FET4 are N-channel MOSFETs. Further, in FIG. 16, a high voltage source VH and a low voltage source VL are used instead of the voltage sources VH and VL of FIG. 15. A potential of the voltage source VH and a potential of the voltage source VL have the following magnitude relation: 0<VL<VH<VIN (A “voltage source” sign is substituted for a “potential” sign). A source of the transistor FET1 is connected to the voltage source VH, and a source of the transistor FET2 is connected to the voltage source VL. A drain of the transistor FET1 and a drain of the transistor FET2 are connected to each other. A source of the transistor FET3 is connected to the voltage source VH, and a source of the transistor FET4 is connected to the voltage source VL. A drain of the transistor FET3 and a drain of the transistor FET4 are connected to each other. Further, a pulse signal GS1 is inputted into a gate of the transistor FET1 and a gate of the transistor FET2, and a pulse signal GS2 is inputted into a gate of the transistor FET3 and a gate of the transistor FET4. The pulse signals GS1 and GS2 are signals whose phases are opposite to each other.
In case of the arrangement of FIG. 16, when a current flows in a direction A, target value of Vcsa=VH, and target value of Vcsb=VL. When a current flows in a direction B, target value of Vcsa=VL, and target value of Vcsb=VH. The pulse signals GS1 and GS2 are ON/OFF signals for causing the currents to flow. In this case, in a pulse period during which the current flows in the direction A or B, a gate-source voltage of each of the transistors is fixed at VH-pulse potential of GS1, pulse potential of GS1-VL, VH-pulse potential of GS2, or pulse potential of GS2-VL. In an initial point of the pulse period, a relatively high voltage is applied between the drain and source of each of the transistors FET1 to FET4, the applied voltage being a difference between each of the potentials VH and VL and an initial potential of each of the auxiliary capacitance wires 24a and 24b. Therefore, regardless of whether the applied voltage is high or low, a drain current has a substantially constant value corresponding to the gate-source voltage. Thereafter, in the direction A, the potential of the auxiliary capacitance wire 24a increases and the potential of the auxiliary capacitance wire 24b decreases. Further, in the direction B, the potential of the auxiliary capacitance wire 24a decreases and the potential of the auxiliary capacitance wire 24b increases. This causes the drain-source voltage of each of the transistors to become low and enter a normal region of switching operation, so that the drain current decreases. There stands a relation of potential 0<VL<VH<VIN, so that, in the initial point of the pulse period, the drain-source voltages of the transistors FET1 to FET4 become lower than the collector-emitter voltages of the transistors Tr1 to Tr4 of FIG. 15. Therefore, when drain currents of the transistors FET1 to FET4 are made lower to some extent, it is possible to cause the transistors FET1 to FET4 to consume less power. This makes it possible to generate less heat.
However, according to the arrangement of FIG. 16, although the voltage source VL is a positive voltage source, the voltage source VL serves as a sink-current-flowing voltage source into which a current keeps on flowing. Therefore, as charge-discharge operation is continued by using the transistors FET1 to FET4, a quantity of positive charges stored in the voltage source VL is not negligible with respect to a capacitance of the voltage source VL. This causes a potential of the voltage source VL to gradually increase and raises such a problem that the voltage source VL no longer functions as a constant voltage source. In such a situation, the potential of the auxiliary capacitance wire 24a and the potential of the auxiliary capacitance wire 24b cannot be controlled accurately, so that the potential Vlca of the sub-pixel electrode 18a and the potential Vlcb of the sub-pixel electrode 18b cannot be controlled accurately.